82583V Datasheet, PDF (217/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
Field
Bit(s)
L1_act_
without_L0s_ 27
rx
L1_Entry_
Latency (LSB) _26:25
(Read Only)
L0S_ENTRY_
LAT
24
L1_Entry_
Latency (MSB) 23
(Read Only)
Reserved
22
Header_log_
order
Reserved
Reserved
Rx_L0s_
Adjustment
Reserved
TXDSCR_
NOSNOOP
TXDSCW_
NOSNOOP
TXD_
NOSNOOP
RXDSCR_
NOSNOOP
RXDSCW_
NOSNOOP
RXD_
NOSNOOP
21
20
19:10
9
8:6
5
4
3
2
1
0
Initial
Value
0b
11b
0b
1b
0b
0b
0b
0x0
1b
0b
0b
0b
0b
0
0b
0b
Description
If set, enables the device to enter ASPM L1 active without any
correlation to L0s_rx.
Determines the idle time of the PCIe link in L0s state before initiating
a transition to L1 state. The initial value is loaded from NVM.
00b = 64 μs
01b = 256 μs
10b = 1 ms
11b = 4 ms
L0s Entry Latency
Set to 0b to indicate L0s entry latency is the same as L0s exit latency.
Set to 1b to indicate L0s entry latency is (L0s exit latency/4).
Latency
000b = 2 μs.
001b = 8 μs.
010b = 1 6μs.
011b = 32 μs.
100b = 64 μs.
101b = 25 6μs.
110b = 1 ms.
111b = 4 ms (default).
Reserved
For proper operation, must be set to 1b by software during
initialization.
When set, indicates a need to change the order of the header log in
the error reporting registers.
Reserved
Reserved
When set to 1b the reply-timer always adds the required L0s
adjustment. When cleared to 0b the adjustment is added only when
Tx L0s is active.
Reserved
Transmit Descriptor Read – No Snoop Indication.
Read directly by transaction layer.
Transmit Descriptor Write – No Snoop Indication.
Read directly by transaction layer.
Transmit Data Read – No Snoop Indication.
Read directly by transaction layer.
Receive Descriptor Read – No snoop indication.
Read directly by transaction layer.
Receive Descriptor Write – No Snoop Indication
Read directly by transaction layer.
Receive Data Write – No Snoop Indication
Read directly by transaction layer.
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