82583V Datasheet, PDF (191/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.1.2
Note:
9.1.3
Registers Byte Ordering
This section defines the structure of registers that contain fields carried over the
network. Some examples are L2, L3, L4 fields.
The following example is used to describe byte ordering over the wire (hex notation):
Last
First
..., 06
05
04
03
02
01
00
where each byte is sent with the Least Significant Bit (LSB) first. That is, the bit order
over the wire for this example is
Last
....
0000 0011
0000 0010
0000 0001
First
0000 0000
The general rule for register ordering is to use host ordering. Using the previous
example, a 6-byte fields (such as, MAC address) is stored in a CSR in the following
manner:
DW address (N)
DW address (N+4)
Byte 3
0x03
Byte 2
0x02
Byte 1
0x01
0x05
Byte 0
0x00
0x04
The following exceptions use network ordering. Using the previous example, a 16-bit
field (such as, EtherType) is stored in a CSR in the following manner:
(DW aligned)
or (WORD aligned)
Byte 3
...
0x00
Byte 2
...
0x01
Byte 1
0x01
...
Byte 0
0x00
...
The following exception uses network ordering:
• All ETherType fields
The normal notation as it appears in text books, etc. is to use network ordering.
Example: Suppose a MAC address of 00-A0-C9-00-00-00. The order on the network is
00, then A0, then C9, etc. However, the host ordering presentation is:
Dword address (N)
Dword address (N+4)
Byte 3
00
...
Byte 2
C9
...
Byte 1
A0
00
Byte 0
00
00
Register Conventions
All registers in the 82583V are defined to be 32 bits. They should be accessed as 32-bit
double-words. There are some exceptions to this rule:
• Register pairs where two 32-bit registers make up a larger logical size.
• Accesses to Flash memory (via expansion ROM space, secondary BAR space, or the
I/O space) can be byte, word or double word accesses.
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