82583V Datasheet, PDF (203/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
Note:
9.2.2.4
output from the NVM is latched into bit 3 of this register via the internal 62.5 MHz clock
and may be accessed by software via reads of this register. See Section 6.3.8 for
details.
Attempts to write to the Flash device when writes are disabled (FWE=01) should not be
attempted. Behavior after such an operation is undefined, and can result in component
and/or system hangs.
EEPROM Read Register - EERD (0x00014; RW)
Note:
9.2.2.5
Field
START
DONE
ADDR
DATA
Bit(s)
0
1
15:2
31:16
Initial
Value
0b
1b
0x0
0x0
Description
Start Read
Writing a 1b to this bit causes the 82583V to read a 16-bit word at the
address stored in the ADDR field from the NVM. The result is stored in
the DATA field. This bit is self-clearing
Read Done
Set to 1b when the word read completes. Set to 0b when the read is
in progress. Writes by software are ignored.
Read Address
This field is written by software along with Start Read to indicate the
word address of the word to read.
Read Data
Data returned from the NVM.
This register is used by software to cause the 82583V to read individual words in the
EEPROM. To read a word, software writes the address to the Read Address field and
simultaneously writes a 1b to the Start Read field. The 82583V reads the word from the
EEPROM and places it in the Read Data field, setting the Read Done field to 1b.
Software can poll this register, looking for a 1b in the Read Done field, and then using
the value in the Read Data field.
When this register is used to read a word from the EEPROM, that word is not written to
any of the 82583V's internal registers even if it is normally a hardware accessed word.
Extended Device Control Register - CTRL_EXT (0x00018; RW)
Field
Reserved
ASDCHK
EE_RST
Reserved
Bit(s)
11:0
12
13
14
Initial
Value
0x0
0b
0b
0b¹
Description
Reserved.
ASD (Auto Speed Detection) Check
Initiate an ASD sequence to sense the frequency of the RX_CLK signal
from the PHY. The results are reflected in STATUS.ASDV. This bit is
self-clearing.
EEPROM Reset
Initiates a reset-like event to the EEPROM function. This causes the
EEPROM to be read as if a PCI_RST_N assertion had occurred.
Note: All device functions should be disabled prior to setting this bit.
This bit is self-clearing.
Reserved
Should be set to 0b.
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