82583V Datasheet, PDF (107/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Interconnects—82583V GbE Controller
6.3.4
6.3.5
6.3.5.1
6.3.6
Note:
Device Operation with an External EEPROM
When the 82583V is connected to an external EEPROM, it provides similar functionality
to its predecessors with the following enhancements:
• Enables a complete parallel interface for read/write to the EEPROM.
• Enables software to specify explicitly the address length, thus eliminating the need
for bit banging access even on an empty EEPROM.
Device Operation with Flash
As previously stated, the 82583V merges the legacy EEPROM and Flash content in a
single Flash device. The 82583V copies the lower section in the Flash device to an
internal shadow RAM. The interface to the shadow RAM is the same as the interface for
an external EEPROM device. This mechanism provides a seamless backward compatible
interface for software to the legacy EEPROM space as if an external EEPROM device is
connected.
The 82583V supports Flash devices with a block erase size of 4 KB. Note that many
Flash vendors are using the term sector differently. This document uses the term Flash
sector for a logic section of 4 KB.
LAN Configuration Sectors
Flash devices require a block erase instruction in case a cell is modified from 0b to 1b.
As a result, in order to update a single byte (or block of data) it is required to erase it
first. The first addresses of the Flash contain the device configuration and must always
be valid. The 82583V maintains two sectors of 4 KB: S0 and S1 for the configuration
content. At least one of these two sectors is valid at any given time or else the 82583V
is set by the hardware default. section 6.3.6 provides more details on the shadow RAM
and the first two sectors.
Shadow RAM
The 82583V includes an internal 4 KB shadow RAM of the first 4 KB Flash sector(s).
When the 82583V is connected to a Flash device the legacy configuration parameters
might reside in any of the first two 4 KB sectors (S0 or S1) in the Flash. The 82583V
copies that data to an internal shadow memory. The shadow RAM emulates a seamless
EEPROM interface to the rest of the 82583V and host CPU. This way the legacy
configuration content is accessible to software and firmware on the same EEPROM
registers as on previous GbE controllers.
Figure 26 shows the shadow RAM mapping and interface relative to the Flash and the
EEPROM. The external EEPROM and the shadow RAM share the same interface. The
82583V might access the EEPROM or shadow RAM according to the setting of the
SELSHAD bit in the EEC register. By hardware default, the SELSHAD bit is set by the
NVMT strapping pin so that the EEPROM is selected in case of external EEPROM and the
shadow RAM is selected in the case of external Flash.
Access to the shadow RAM uses the same interface as the external EEPROM with the
exception that bit banging is not supported for the shadow RAM.
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