82583V Datasheet, PDF (317/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Programing Interface—82583V GbE Controller
10.1.5.1.8
Link Control, Offset 0xF0, (RO)
This register controls PCIe link specific parameters.
Bits
R/R
1:0
RW
2
RO
3
RW
4
RO
5
RO
6
RW
7
RW
15:8
RO
Default
Description
Active State Link PM Control
This field controls the active state PM supported on the link. Defined
encodings are:
00b
00b = PM disabled.
01b = L0s entry supported.
10b = Reserved.
11b = L0s and L1 supported.
0b
Reserved.
0b
Read Completion Boundary.
0b
Link Disable
Not applicable for end-point devices, hardwired to 0b.
0b
Retrain Clock
Not applicable for end-point devices, hardwired to 0b.
Common Clock Configuration
When set, indicates that the 82583V and the component at the other end of
0b
the link are operating with a common reference clock. A value of 0b indicates
that they operate with an asynchronous clock. This parameter affects the L0s
exit latencies.
Extended Sync
0b
This bit, when set, forces extended Tx of FTS ordered set in FTS and extra
TS1 at exit from L0s prior to enter L0.
0x0
Reserved.
10.1.5.1.9
Link Status, Offset 0xF2, (RO)
This register provides information about PCIe link-specific parameters. This is a read-
only register.
Bits
3:0
9:4
10
11
12
15:13
R/W
RO
RO
RO
RO
HwInit
RO
Default
Description
0001b
000001b
0b
0b
1b
0000b
Link Speed
Indicates the negotiated link speed. 0001b is the only defined speed, which is
2.5 Gb/s.
Negotiated Link Width
Indicates the negotiated width of the link.
Relevant encoding for the 82583V is:
000001b x1
Link Training Error
Indicates that a link training error has occurred.
Link Training
Indicates that link training is in progress.
Slot Clock Configuration
When set, indicates that the 82583V uses the physical reference clock that
the platform provides on the connector. This bit must be cleared if the 82583V
uses an independent clock. Slot Clock Configuration bit is loaded from the
Slot_Clock_Cfg NVM bit.
Reserved
317