82583V Datasheet, PDF (124/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Inline Functions
7.1.5.1
Note:
Buffer Addresses [3:0] (4 x 64 bit)
The physical address of each buffer is written in the Buffer Addresses fields. The sizes
of these buffers are statically defined by BSIZE0-BSIZE3 in the PSRCTL register.
Software Notes:
• All buffers' addresses in a packet split descriptor must be word aligned.
• Packet header can't span across buffers, therefore, the size of the first buffer must
be larger than any expected header size. Otherwise the packet will not be split.
• If software sets a buffer size to zero, all buffers following that one should be set to
zero as well. Pointers in the packet split receive descriptors to buffers with a zero
size should be set to any address, but not to NULL pointers. Hardware does not
write to this address.
• When configured to packet split and a given packet spans across two or more
packet split descriptors, the first buffer of any descriptor (other than the first one)
is not used.
7.1.5.2
Note:
DD (1-Bit, Offset 8.0)
The software device driver might use the DD bit from the Status field to determine
when a descriptor has been used. Therefore, the software device driver must ensure
that the Least Significant B (LSB) of Buffer Address 1 is zero. This should not be an
issue, since the buffers should be page aligned for the packet split feature to be useful.
Any software device driver that cannot align buffers should not be using this descriptor
format.
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