82583V Datasheet, PDF (197/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
Category
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Offset
0x02430
0x03410
0x03418
0x03420
0x03428
0x03430
0x10000 -
0x17FFF
0x01008
Alias
Offset
N/A
0x08010
0x08018
N/A
N/A
N/A
N/A
N/A
Abbreviation
RDFPC
TDFH
TDFT
TDFHS
TDFTS
TDFPC
PBM
PBS
Name
Receive Data FIFO Packet Count
Transmit Data FIFO Head Register
Transmit Data FIFO Tail Register
Transmit Data FIFO Head Saved Register
Transmit Data FIFO Tail Saved Register
Transmit Data FIFO Packet Count
RW
RW
RW
RW
RW
RW
RW
Link to
Page
page 298
page 298
page 298
page 299
page 299
page 299
Packet Buffer Memory
RW page 299
Packet Buffer Size
RW page 300
Note:
Certain registers maintain an alias address designed for backward compatibility with
software written for previous devices. For these registers, the alias address is shown in
Table 49. Those registers can be accessed by software at either the new offset or the
alias offset. It is recommended that software written solely for the 82583V, use the
new address offset.
9.2.2
General Register Descriptions
9.2.2.1
Device Control Register - CTRL (0x00000 / 0x00004; RW)
Field
FD
Reserved
GIO Master
Disable
Reserved
Reserved
ASDE
SLU
Reserved
Bit(s)
0
1
2
3
4
5
6
7
Initial
Value
1b¹
0b
0b
1b
0b
0b¹
0b¹
0b
Description
Full Duplex
0b = Half duplex
1b = Full duplex. Controls the MAC duplex setting when explicitly set
by software.
Reserved
Write as 0b for future compatibility.
When set, the 82583V blocks new master requests using this
function. Once no master requests are pending by this function, the
GIO Master Enable Status bit is set.
Reserved
Set to 1b.
Reserved
Write as 0b for future compatibility.
Auto-Speed Detection Enable
When set to 1b, the MAC ignores the speed indicated by the PHY and
attempts to automatically detect the resolved speed of the link and
configure itself appropriately.
This bit must be set to 0b in the 82583V.
Set Link Up
The Set Link Up bit MUST be set to 1b to permit the MAC to recognize
the link signal from the PHY, which indicates the PHY has gotten the
link up, and to receive and transmit data.
See Section 6.2.3 for more information about auto-negotiation and
link configuration in the various modes.
Set link up is normally initialized to 0b. However, if the APM Enable bit
is set in the NVM then it is initialized to 1b.
Reserved.
Must be set to 0b.
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