82583V Datasheet, PDF (342/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Design Considerations
11.6
11.6.1
4. Routing any other trace parallel to and close to one of the differential traces.
Crosstalk getting onto the receive channel will cause degraded long cable BER.
Crosstalk getting onto the transmit channel can cause excessive EMI emissions and
can cause poor transmit BER on long cables. At a minimum, other signals should be
kept 0.3 inches from the differential traces.
5. Routing one pair of differential traces too close to another pair of differential traces.
After exiting the Ethernet silicon, the trace pairs should be kept 0.3 inches or more
away from the other trace pairs. The only possible exceptions are in the vicinities
where the traces enter or exit the magnetics, the RJ-45 connector, and the
Ethernet silicon.
6. Use of a low-quality magnetics module.
7. Re-use of an out-of-date physical layer schematic in a Ethernet silicon design. The
terminations and decoupling can be different from one PHY to another.
8. Incorrect differential trace impedances. It is important to have ~100 Ω impedance
between the two traces within a differential pair. This becomes even more
important as the differential traces become longer. To calculate differential
impedance, many impedance calculators only multiply the single-ended impedance
by two. This does not take into account edge-to-edge capacitive coupling between
the two traces. When the two traces within a differential pair are kept close to each
other, the edge coupling can lower the effective differential impedance by 5 Ω to
20 Ω. Short traces have fewer problems if the differential impedance is slightly off
target.
82583V Power Supplies
The 82583V requires three power rails: 3.3 V dc, 1.9 V dc, and 1.05 V dc (see
section 8.4). A central power supply can provide all the required voltage sources or the
power can be derived from the 3.3 V dc supply and regulated locally using external
regulators. If the LAN wake capability is used, all voltages must remain present during
system power down. Local regulation of the LAN voltages from system 3.3 Vmain and
3.3 Vaux voltages is recommended. Refer to section 11.3 and section 11.5 for detailed
information about power supply sequencing rules and intended design options for
power solutions.
External voltage regulators need to generate the proper voltage, supply current
requirements (with adequate margin), and provide the proper power sequencing.
82583V GbE Controller Power Sequencing
Designs must comply with power sequencing requirements to avoid latch-up and
forward-biased internal diodes (see Figure 58).
The general guideline for sequencing is:
1. Power up the 3.3 V dc rail.
2. Power up the 1.9 V dc next.
3. Power up the 1.05 V dc rail last.
For power down, there is no requirement (only charge that remains is stored in the
decoupling capacitors).
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