82583V Datasheet, PDF (299/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.9.9
This register’s address has been moved from where it was located in the previous
devices. However, for backwards compatibility, this register can also be accessed at its
alias offset of 0x08018. In addition, with the 82583V, the value in this register contains
the offset of the transmit FIFO head relative to the beginning of the entire PBM space.
Alternatively, with the previous devices, the value in this register contains the relative
offset to the beginning of the transmit FIFO space (within the PBM space).
Transmit Data FIFO Head Saved Register - TDFHS (0x03420; RW)
9.2.9.10
Field
FIFO Head
Reserved
Bit(s)
12:0
31:13
Initial
Value
0x600¹
0x0
Description
A saved value of the Transmit FIFO Head Pointer.
Reads as 0x0. Should be written to 0x0 for future compatibility.
1. The initial value equals PBA.RXA times 128.
This register stores a copy of the Transmit Data FIFO Head register if the internal
register needs to be restored. This register is available for diagnostic purposes only,
and should not be written during normal operation.
Transmit Data FIFO Tail Saved Register - TDFTS (0x03428; RW)
9.2.9.11
Field
FIFO Tail
Reserved
Bit(s)
12:0
31:13
Initial
Value
0x600¹
0x0
Description
A saved value of the Transmit FIFO Tail Pointer.
Reads as 0x0. Should be written to 0x0 for future compatibility.
1. The initial value equals PBA.RXA times 128.
This register stores a copy of the Receive Data FIFO Tail register if the internal register
needs to be restored. This register is available for diagnostic purposes only, and should
not be written during normal operation.
Transmit Data FIFO Packet Count - TDFPC (0x03430; RW)
9.2.9.12
Field
Bit(s)
TX FIFO
Packet Count
Reserved
12:0
31:13
Initial
Value
0x0
0x0
Description
The number of packets to be transmitted that are currently in the TX
FIFO.
Reads as 0x0. Should be written to 0x0 for future compatibility.
This register reflects the number of packets to be transmitted that are currently in the
transmit FIFO. This register is available for diagnostic purposes only, and should not be
written during normal operation.
Packet Buffer Memory - PBM (0x10000 - 0x17FFF; RW)
Field
FIFO Data
Bit(s)
31:0
Initial
Value
X
Packet Buffer Data
Description
299