82583V Datasheet, PDF (367/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Board Layout and Schematic Checklists—82583V GbE Controller
Table 64. Schematic Checklist
Section
Check Items
Remarks
General
PCIe Interface
Support Pins
Obtain the most recent documentation and
specification updates.
Observe instructions for special pins needing
pull-up or pull-down resistors.
Connect PCIe interface pins to corresponding
pins on an upstream PCIe device.
Place AC coupling capacitors (0.1 μF) near the
PCIe transmitter.
Connect PECLKn and PECLKp to 100 MHz PCIe
system clock.
Connect PE_RST_N to PLTRST# on an
upstream PCIe device.
Connect PE_WAKE_N to PE_WAKE# on an
upstream PCIe device.
Connect pin 28 DEV_OFF_N to
SUPER_IO_GP_DISABLE# or a pull-up with a
1 KΩ resistor.
Pull-down pin 48, RSET, with a 4.99 KΩ 1%
resistor.
Pull-up pin 39, AUX_PWR, with a 10 KΩ
resistor if the power supplies are derived from
always on auxiliary power rails.
Pull-down reserved pins RSVD2_PD,
RSVD3_PD, and RSVD7_PD with 10 KΩ
resistors.
Pull-up reserved pins RSVD5_PU, RSVD6_PU,
RSVD8_PU, RSVD9_PU, RSVD34_PU,
RSVD35_PU, and RSVD36_PU with 10 KΩ
resistors.
Pull-down pin 29, TEST_EN, with a 1 KΩ
resistor.
Documents are subject to frequent change.
Size 0402, X7R is recommended.
This is required by the PCIe interface.
This is required for proper device initialization.
This is required to enable Wake on LAN functionality
required for advanced power management.
Connect to a super I/O pin that retains its value during
PCIe reset, is driven from the resume well and defaults
to one on power-up.
If device off functionality is not needed, then
DEV_OFF_N should be connected with an external pull-
up resistor. Ensure pull-ups are connected to aux
power.
This is required by the PCIe and MDI interfaces.
This pin impacts operation if the 82583V advertises D3
cold wakeup support on the PCIe bus.
Ensure pull-ups are connected to auxiliary power.
Required for normal operation.
Required for normal operation.
This is required to prevent the device from going into
test mode during normal operation.
This pin must be driven high during the XOR test.
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