82583V Datasheet, PDF (88/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
Table 29. Allocation of FC Credits
6.1.4.2
6.1.4.3
6.1.4.4
Credit Type
Operations
Posted Request Header (PH)
Posted Request Data (PD)
Non-Posted Request Header (NPH)
Non-Posted Request Data (NPD)
Completion Header (CPLH)
Completion Data (CPLD)
Target write (1 unit)
Message (1 unit)
Target write (Length/16B=1)
Message (1 unit)
Target read (1 unit)
Configuration read (1 unit)
Configuration write (1 unit)
Configuration write (1 unit)
Read completion (N/A)
Read completion (N/A)
Number Of Credits
2 units
16 credits (for 256 bytes)
2 units
2 units
Infinite (accepted immediately)
Infinite (accepted immediately)
Rules for FC updates:
• The 82583V maintains two credits for NPD at any given time. It increments the
credit by one after the credit is consumed and sends an UpdateFC packet as soon
as possible. UpdateFC packets are scheduled immediately after a resource is
available.
• The 82583V provides two credits for PH (such as for two concurrent target writes)
and two credits for NPH (such as for two concurrent target reads). UpdateFC
packets are scheduled immediately after a resource becomes available.
• The 82583V follows the PCIe recommendations for frequency of UpdateFC FCPs.
Upstream Flow Control Tracking
The 82583V issues a master transaction only when the required FC credits are
available. Credits are tracked for posted, non-posted, and completions (the later to
operate against a switch).
Flow Control Update Frequency
In any case, UpdateFC packets are scheduled immediately after a resource becomes
available.
When the link is in the L0 or L0s link state, update FCPs for each enabled type of non-
infinite FC credit must be scheduled for transmission at least once every 30 µs (-0%/
+50%), except when the Extended Sync bit of the Control Link register is set, in which
case the limit is 120 µs (-0%/+50%).
Flow Control Timeout Mechanism
The 82583V implements the optional FC update timeout mechanism. The mechanism is
activated when the link is in L0 or L0s link state. It uses a timer with a limit of 200 µs (-
0%/+50%), where the timer is reset by the receipt of any init or update FCP.
Alternately, the timer can be reset by the receipt of any DLLP.
After timer expiration, the mechanism instructs the PHY to retrain the link (via the
LTSSM recovery state).
88