82583V Datasheet, PDF (263/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.7.38 Total Octets Received - TORL (0x040C0; R)
9.2.7.39 Total Octets Received - TORH (0x040C4; R)
Note:
9.2.7.40
Field
TORL
TORH
Bit(s)
31:0
31:0
Initial
Value
0x0
0x0
Description
Number of total octets received – lower 4 bytes.
Number of total octets received – upper 4 bytes.
These registers make up a logical 64-bit register that counts the total number of octets
received. This register must be accessed using two independent 32-bit accesses. This
register resets whenever the upper 32 bits are read (TORH). In addition, it sticks at
0xFFFF_FFFF_FFFF_FFFF when the maximum value is reached.
All packets received have their octets summed into this register, regardless of their
length, whether they are erred, or whether they are flow control packets. This register
includes bytes received in a packet from the <Destination Address> field through the
<CRC> field, inclusively. This register only increments if receives are enabled.
Broadcast rejected packets are counted in this counter (in contradiction to all other
rejected packets that are not counted).
Total Octets Transmitted - TOT (0x040C8; RW)
Field
TOTL
TOTH
Bit(s)
31:0
31:0
Initial
Value
0x0
0x0
Description
Number of total octets transmitted – lower 4 bytes.
Number of total octets transmitted – upper 4 bytes.
These registers make up a logical 64-bit register that counts the total number of octets
transmitted. This register must be accessed using two independent 32-bit accesses.
This register resets whenever the upper 32 bits are read (TOTH). In addition, it sticks
at 0xFFFF_FFFF_FFFF_FFFF when the maximum value is reached.
All transmitted packets have their octets summed into this register, regardless of their
length or whether they are flow control packets. This register includes bytes
transmitted in a packet from the <Destination Address> field through the <CRC> field,
inclusively.
Octets transmitted as part of partial packet transmissions (for example, collisions in
half-duplex mode) are not included in this register. This register only increments if
transmits are enabled.
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