82583V Datasheet, PDF (110/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
Note:
Note:
6.3.7.3
6.3.8
6.3.8.1
6.3.8.2
When software accesses the EEPROM or Flash spaces via the bit banging interface, it
should follow these steps:
1. Write a 1b to the Request bit in the FLA or EEC registers.
2. Poll the Grant bit in the FLA or EEC registers until its ready.
3. Access the NVM using the direct interface to its signaling via the EEC or FLA
registers.
4. When access completes, software should clear the Request bit.
Following a write or erase instruction, software should clear the Request bit only after it
checked that the cycles were completed by the NVM.
CSR Mapped Firmware Interface
Firmware might access the NVM or shadow RAM via the NVM Control registers in the
CSR space with the following capabilities:
• Word read and write accesses to the EEPROM or shadow RAM via the EECTL and
EEDATA registers.
• Read and write DMA and block erase to the Flash interface via the FLCTL and
FLDATA registers. Flash accesses are mapped to the physical NVM at offset 0x0.
Note that nominal accesses to the first two 4 KB sectors should be addressed to the
shadow RAM via the EEPROM interface.
NVM Write and Erase Sequence
Software Flow to the Bit Banging Interface
When software accesses the EEPROM or Flash CSR registers to the bit banging interface
it should follow these steps:
1. Write a 1b to the Request bit in the FLA or EEC registers.
2. Poll the Grant bit in the FLA or EEC registers until its ready.
3. Access the NVM using the direct interface to its signaling via the EEC or FLA
registers.
4. When access is achieved, software should clear the Request bit. Note that following
a write or erase instruction, software should clear the Request bit only after it
checked that the cycles were completed by the NVM.
Software Byte Program Flow to the EEPROM Interface
Software initiates a write cycle to the NVM on the parallel EEPROM as follows:
1. Poll the Done bit in the EEWR register until its set.
2. Write the data word, its address, and the Start bit to the EEWR register.
As a response, hardware executes the following steps:
Case 1 - The 82583V is connected to a physical EEPROM device:
1. Initiate an autonomous write enable instruction.
2. Initiate the program instruction right after the enable instruction.
3. Poll the EEPROM status until programming completes.
4. Set the Done bit in the EEWR register.
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