82583V Datasheet, PDF (160/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Inline Functions
7.4
7.4.1
7.4.2
UDP Header
• UDP length: (last frame payload bytes + HDRLEN) - TUCSS
• UDP Checksum
Interrupts
The 82583V supports the following interrupt modes:
• PCI legacy interrupts
• PCI MSI - Message Signaled Interrupts
Legacy and MSI Interrupt Modes
In legacy and MSI modes, an interrupt cause is reflected by setting one of the bits in
the ICR register, where each bit reflects one or more causes. This description of ICR
register provides the mapping of interrupt causes (for example, a specific Rx queue
event or a LSC event) to bits in the ICR.
Mapping of causes relating to the Tx and Rx queues as well as non-queue causes in this
mode is not configurable. Each possible queue interrupt cause (such as the Rx queue,
Tx queue or any other interrupt source) has an entry in the ICR.
The following configuration and parameters are involved:
• The ICR[31:0] bits are allocated to specific interrupt causes
Registers
The interrupt logic consists of the registers listed in the following table, plus the
registers associated with MSI signaling.
Register
Acronym
Interrupt Cause
ICR
Interrupt Cause Set
ICS
Interrupt Mask Set/Read IMS
Interrupt Mask Clear
IMC
Interrupt Auto Clear
EIAC
Interrupt Auto Mask
IAM
Function
Records all interrupt causes - an interrupt is signaled when
unmasked bits in this register are set.
Enables software to set bits in the Interrupt Cause register.
Sets or reads bits in the interrupt mask.
Clears bits in the Interrupt mask.
Enables bits in the ICR and IMS without a read or write of the
ICR.
Enables bits in the IMS to be set automatically.
Interrupt Cause Registers (ICR)
This register records the interrupts causes to provide to the software information on
the interrupt source.
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