HD6433044 Datasheet, PDF (93/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

4.5 Stack Status after Exception Handling
Figure 4-6 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP-4
SP-3
SP-2
SP-1
SP (ER7) ^→
Stack area
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
CCR
PC _E
PC _H
PC _L
Even address
Before exception handling
After exception handling
Pushed on stack
Legend
PCE: Bits 23 to 16 of program counter (PC)
PCH: Bits 15 to 8 of program counter (PC)
PCL: Bits 7 to 0 of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC indicates the address of the first instruction that will be executed after return.
2. Registers must be saved in word or longword size at even addresses.
Figure 4-6 Stack after Completion of Exception Handling
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