HD6433044 Datasheet, PDF (4/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

2.9 Basic Operational Timing............................................................................................... 51
2.9.1 Overview......................................................................................................... 51
2.9.2 On-Chip Memory Access Timing................................................................... 51
2.9.3 On-Chip Supporting Module Access Timing ................................................. 53
2.9.4 Access to External Address Space.................................................................. 54
Section 3 MCU Operating Modes........................................................................... 55
3.1 Overview......................................................................................................................... 55
3.1.1 Operating Mode Selection .............................................................................. 55
3.1.2 Register Configuration.................................................................................... 56
3.2 Mode Control Register (MDCR) .................................................................................... 57
3.3 System Control Register (SYSCR)................................................................................. 58
3.4 Operating Mode Descriptions......................................................................................... 60
3.4.1 Mode 1 ............................................................................................................ 60
3.4.2 Mode 2 ............................................................................................................ 60
3.4.3 Mode 3 ............................................................................................................ 60
3.4.4 Mode 4 ............................................................................................................ 60
3.4.5 Mode 5 ............................................................................................................ 60
3.4.6 Mode 6 ........................................................................................................... 60
3.4.7 Mode 7 ........................................................................................................... 61
3.5 Pin Functions in Each Operating Mode.......................................................................... 61
3.6 Memory Map in Each Operating Mode.......................................................................... 61
Section 4 Exception Handling.................................................................................. 71
4.1 Overview......................................................................................................................... 71
4.1.1 Exception Handling Types and Priority.......................................................... 71
4.1.2 Exception Handling Operation ....................................................................... 71
4.1.3 Exception Vector Table................................................................................... 72
4.2 Reset ............................................................................................................................... 73
4.2.1 Overview......................................................................................................... 73
4.2.2 Reset Sequence ............................................................................................... 73
4.2.3 Interrupts after Reset....................................................................................... 76
4.3 Interrupts......................................................................................................................... 77
4.4 Trap Instruction............................................................................................................... 78
4.5 Stack Status after Exception Handling ........................................................................... 79
4.6 Notes on Stack Usage ..................................................................................................... 80
Section 5 Interrupt Controller................................................................................... 81
5.1 Overview......................................................................................................................... 81
5.1.1 Features........................................................................................................... 81
5.1.2 Block Diagram................................................................................................ 82