HD6433044 Datasheet, PDF (401/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Note on Synchronous Preset: When channels are synchronized, if a TCNT value is modified by
byte write access, all 16 bits of all synchronized counters assume the same value as the counter
that was addressed.
(Example) When channels 2 and 3 are synchronized
• Byte write to channel 2 or byte write to channel 3
TCNT2
W
X
Write A to upper byte
of channel 2
TCNT2
A
X
TCNT3
Y
Z
Upper byte Lower byte
Write A to lower byte
of channel 3
TCNT3
A
X
Upper byte Lower byte
TCNT2
Y
A
TCNT3
Y
A
Upper byte Lower byte
Note^Won ^dSetu^itp o^t f R^heset-S^ly²nchron^dized^itPW^t M^hMode^{l 3}and Complementary PWM Mode: When
setting bits CMD1 and CMD0 in TFCR, take the following precautions:
• Write to bits CMD1 and CMD0 only when TCNT3 and TCNT4 are stopped.
• Do not switch directly between reset-synchronized PWM mode and complementary PWM
mode. First switch to normal mode (by clearing bit CMD1 to 0), then select reset-
synchronized PWM mode or complementary PWM mode.
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