HD6433044 Datasheet, PDF (148/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Wait Mode in Areas Where Wait-State Controller is Disabled
External three-state access areas in which the wait-state controller is disabled (ASTn = 1, WCEn =
0) operate in pin wait mode 0. The other wait modes are unavailable. The settings of bits WMS1
and WMS0 are ignored in these areas.
Pin Wait Mode 0: Wait states can only be inserted by WAIT pin control. During access to an
external three-state-access area, if the WAIT pin is low at the fall of the system clock (ø) in the T₂
state, a wait state (T_W) is inserted. If the WAIT pin remains low, wait states continue to be
inserted until the WAIT signal goes high. Figure 6-12 shows the timing.
Inserted by WAIT signal
T₁
T₂
T_W
T_W
T₃
ø
*
*
*
WAIT pin
Address bus
External address
AS
Read
access
RD
Data bus
Read data
Write
access
HWR, LWR
Data bus
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6-12 Pin Wait Mode 0
134