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HD6433044 Datasheet, PDF (404/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer | |||
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Table 10-11 (c) ITU Operating Modes (Channel 2)
Register Settings
TSNC
TMDR
TFCR
TOCR
TOER
TIOR2
TCR2
Reset-
Comple- Synchro-
Output
Synchro-
mentary nized Buffer-
Level Master
Clear
Clock
Operating Mode
nization MDF FDIR PWM
PWM PWM ing XTGD Select Enable IOA
IOB
Select
Select
Synchronous preset SYNC2 = 1
â
â
â
â
â
â
â
PWM mode
â PWM2 = 1 â
â
â
â
â
â
â
*
Output compare A
â PWM2 = 0 â
â
â
â
â
â
IOA2 = 0
Other bits
unrestricted
Output compare B
â
â
â
â
â
â
â
IOB2 = 0
Other bits
unrestricted
Input capture A
â PWM2 = 0 â
â
â
â
â
â
IOA2 = 1
Other bits
unrestricted
Input capture B
â PWM2 = 0 â
â
â
â
â
â
IOB2 = 1
Other bits
unrestricted
Counter By compare
clearing match/input
capture A
â
â
â
â
â
â
â
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
â
â
â
â
â
â
â
CCLR1 = 1
CCLR0 = 0
Syn-
SYNC2 = 1
â
chronous
clear
â
â
â
â
â
â
CCLR1 = 1
CCLR0 = 1
Phase counting
MDF = 1
â
â
â
â
â
â
â
mode
Legend: Setting available (valid). â Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
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