HD6433044 Datasheet, PDF (191/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

7.3.4 Interval Timing
To use the refresh controller as an interval timer, clear the PSRAME and DRAME both to 0. After
setting RTCOR, select a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit
to 1.
Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag
in RTCSR is set to 1 by a compare match signal output when the RTCOR and RTCNT values
match. The compare match signal is generated in the last state in which the values match (when
RTCNT is updated from the matching value to a new value). Accordingly, when RTCNT and
RTCOR match, the compare match signal is not generated until the next counter clock pulse.
Figure 7-19 shows the timing.
ø
RTCNT
N
RTCOR
Compare
match signal
CMF flag
H'00
N
Figure 7-19 Timing of Setting of CMF Flag
Operation in Power-Down State: The interval timer function operates in sleep mode. It does not
operate in hardware standby mode. In software standby mode RTCNT and RTMCSR bits 7 and 6
are initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to
software standby mode.
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