HD6433044 Datasheet, PDF (186/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

7.3.3 Pseudo-Static RAM Refresh Control
Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is
determined as in a DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in
RTMCSR. The numbers of states required for pseudo-static RAM read/write cycles and refresh
cycles are the same as for DRAM (see table 7-4). The state transitions are as shown in figure 7-3.
Pseudo-Static RAM Control Signals: Figure 7-15 shows the control signals for pseudo-static
RAM read, write, and refresh cycles.
ø
Address
bus
CS ₃
RD
HWR
LWR
RFSH
AS
Read cycle
Write cycle *
Refresh cycle
Area 3 top address
Note: * 16-bit access
Figure 7-15 Pseudo-Static RAM Control Signal Output Timing
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