HD6433044 Datasheet, PDF (193/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Contention between RTCNT Write and Increment: If an increment pulse occurs in the T₃ state
of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 7-21.
ø
Address bus
Internal
write signal
RTCNT
input clock
RTCNT
RTCNT write cycle by CPU
T₁
T₂
T₃
RTCNT address
N
M
Counter write data
Figure 7-21 Contention between RTCNT Write and Increment
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