HD6433044 Datasheet, PDF (799/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

TCNT—Timer Counter
H'A9 (read),
H'A8 (write)
WDT
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
RSTCSR—Reset Control/Status Register
H'AB (read),
H'AA (write)
Bit
7
6
5
4
3
2
1
WRST RSTOE —
—
—
—
—
Initial value
0
0
1
1
1
1
1
Read/Write R/(W)* R/W
—
—
—
—
—
Reset output enable
0 External output of reset signal is disabled
1 External output of reset signal is enabled
Watchdog timer reset
0 [Clearing condition]
• Reset signal input at RES pin
• When WRST= "1", write "0" after reading WRST flag
1 [Setting condition]
TCNT overflow generates a reset signal
Note: * Only 0 can be written in bit 7, to clear the flag.
WDT
0
—
1
—
792