HD6433044 Datasheet, PDF (244/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Figure 8-18 shows the timing when the DMAC is activated by the falling edge of DREQ in block
transfer mode.
ø
DREQ
End of 1 block transfer
DMAC cycle
CPU cycle
DMAC cycle
T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂
Address
bus
RD
HWR , LWR
TEND
Next sampling
Minimum 4 states
Figure 8-18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode
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