HD6433044 Datasheet, PDF(593/867 Page) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

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HD6433044 Datasheet, PDF (593/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

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Automatic Alignment of SCI Bit Rate

Start

bit

D0

D1

D2

D3

D4

D5

D6

This low period (9 bits) is measured (H'00 data)

D7 Stop

bit

High for at

least 1 bit

Figure 18-11 Measurement of Low Period in Data Transmitted from Host

When started in boot mode, the H8/3048F measures the low period in asynchronous SCI data

transmitted from the host (figure 18-11). The data format is eight data bits, one stop bit, and no

parity bit. From the measured low period (nine bits), the H8/3048F computes the hostâs

transmission bit rate. After aligning its own bit rate, the H8/3048F sends the host one byte of H'00

data to indicate that bit-rate alignment is completed. The host should check that this alignment-

completed indication is received normally, then transmit one H'55 byte. If the host does not receive

a normal alignment-completed indication, the H8/3048F should be reset, then restarted in boot

mode to measure the low period again. There may be some alignment error between the hostâs and

H8/3048Fâs bit rates, depending on the hostâs bit rate and the H8/3048Fâs system clock frequency.

To have the SCI operate normally, set the hostâs bit rate to a value 2400, 4800 or 9600 bps*1. Table

18-13 lists typical host bit rates and indicates the clock-frequency ranges over which the H8/3048F

can align its bit rate automatically. Boot mode should be used within these frequency ranges.*2

Table 18-13 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by

H8/3048F

Host Bit Rate*1

9600 bps

4800 bps

2400 bps

System Clock Frequencies Permitting

Automatic Bit-Rate Alignment by H8/3048F

8 MHz to 16 MHz

4 MHz to 16 MHz

2 MHz to 16 MHz

Notes: 1. Host bit rate settings are 2400, 4800, and 9600 bps; no other settings should be used.

2. Although the H8/3048F may perform automatic bit-rate alignment with combinations

of bit rate and system clock other than those shown in table 18-13, there may be a

discrepancy between the bit rates of the host and the H8/3048F, preventing subsequent

transfer from being performed normally. Boot mode execution should therefore be

confined to the range of combinations shown in table 18-13.

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