HD6433044 Datasheet, PDF (704/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

21.4.2 Refresh Controller Bus Timing
Refresh controller bus timing is shown as follows:
• DRAM bus timing
Figures 21-10 to 21-15 show the DRAM bus timing in each operating mode.
• PSRAM bus timing
Figures 21-16 and 21-17 show the pseudo-static RAM bus timing in each operating mode.
ø
A₉ to A₁
AS
CS₃ (RAS)
RD (CAS)
HWR (UW),
LWR (LW )
(read)
HWR (UW),
LWR (LW )
(write)
RFSH
D₁₅ to D₀
(read)
D₁₅ to D₀
(write)
T₁
t_AD
t_RAD1
t_AS1
T₂
T₃
t_AD
t_RAH
t_ASD
t_AS1
t_RAD3
t_SD
t_CAS
t_RP
t_CRP
t_ASD
t_RAC
t_AA
t_CAC
t_SD
t_WDH
t_WDS3
t_RDS
t_RDH
Figure 21-10 DRAM Bus Timing (Read/Write): Three-State Access
— 2WE Mode —
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