HD6433044 Datasheet, PDF (225/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at
each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and
a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to
H'0000.
Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and
external request signals.
For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).
Figure 8-5 shows a sample setup procedure for idle mode.
Idle mode setup
1. Set the source and destination addresses
in MAR and IOAR. The transfer direction is deter-
mined automatically from the activation source.
Set source and
destination addresses
1
2. Set the transfer count in ETCR.
3. Read DTCR while the DTE bit is cleared to 0.
4. Set the DTCR bits as follows.
• Select the DMAC activation source with bits
DTS2 to DTS0.
Set transfer count
2
• Set the DTIE and RPE bits to 1 to select idle mode.
• Select byte size or word size with the DTSZ bit.
• Set the DTE bit to 1 to enable the transfer.
Read DTCR
3
Set DTCR
4
Idle mode
Figure 8-5 Idle Mode Setup Procedure (Example)
211