HD6433044 Datasheet, PDF (857/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Table D-1 Port States (cont)
Pin
Name
Mode
Reset
Hardware Software
Standby Standby
Mode
Mode
Bus-
Released
Mode
Program
Execution,
Sleep Mode
P5₃ to P5₀
1 to 4
5, 6
L
T
T
T
T
T
keep
T
A₁₉ to A₁₆
Input port
(DDR = 0)
T
T
A₁₉ to A₁₆
(DDR = 1)
7
T
T
keep
—
I/O port
P6₀
1 to 6
T
T
keep
keep
I/O port
WAIT
7
T
T
keep
—
I/O port
P6₁
1 to 6
T
T
keep
T
(BRLE = 0)
T
(BRLE = 1)
I/O port
BREQ
7
T
T
keep
—
I/O port
P6₂
1 to 6
T
T
keep
L
(BRLE = 0)
H
(BRLE = 1)
I/O port
(BRLE = 0)
or BACK
(BRLE = 1)
7
T
T
keep
—
I/O port
P6₆ to P6₃ 1 to 6
H*³
T
T
T
AS, RD,
HWR, LWR
7
T
T
keep
—
I/O port
P7₇ to P7₀
P8₀
1 to 7
1 to 6
T
T
T
T*
Input port
T
T
keep
keep
I/O port
(RFSHE = 0) (RFSHE = 0) (RFSHE = 0)
RFSH
H
or RFSH
(RFSHE = 1) (RFSHE = 1) (RFSHE = 1)
7
T
T
keep
—
I/O port
Legend
H: High
L: Low
T: High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
Note: * The bus cannot be released in mode 7.
850