HD6433044 Datasheet, PDF (779/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

TIER0—Timer Interrupt Enable Register 0
Bit
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
Read/Write
—
—
—
—
H'66
ITU0
3
2
1
0
—
OVIE IMIEB IMIEA
1
0
0
0
—
R/W R/W R/W
Input capture/compare match interrupt enable A
0 IMIA interrupt requested by IMFA flag is disabled
1 IMIA interrupt requested by IMFA flag is enabled
Input capture/compare match interrupt enable B
0 IMIB interrupt requested by IMFB flag is disabled
1 IMIB interrupt requested by IMFB flag is enabled
Overflow interrupt enable
0 OVI interrupt requested by OVF flag is disabled
1 OVI interrupt requested by OVF flag is enabled
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