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HD6433044 Datasheet, PDF (790/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer
TOCR—Timer Output Control Register
Bit
7
6
5
4
—
—
— XTGD
Initial value
1
1
1
1
Read/Write
—
—
—
R/W
H'91
3
2
—
—
1
1
—
—
ITU (all channels)
1
OLS4
1
R/W
0
OLS3
1
R/W
Output level select 3
0 TIOCB3, TOCXA4, and TOCXB4 outputs are inverted
1 TIOCB3, TOCXA4, and TOCXB4 outputs are not inverted
Output level select 4
0 TIOCA3, TIOCA4, and TIOCB4 outputs are inverted
1 TIOCA3, TIOCA4, and TIOCB4 outputs are not inverted
External trigger disable
0 Input capture A in channel 1 is used as an external trigger signal in
reset-synchronized PWM mode and complementary PWM mode*
1 External triggering is disabled
Note: * When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0, disabling ITU
output.
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