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HD6433044 Datasheet, PDF (678/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer
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Table 21-7 Timing of On-Chip Supporting Modules
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.15 V to 5.5 V, AVCC = 3.15 V to 5.5 V, VREF = 3.15 V to AVCC,
VSS = AVSS = 0 V, ø = 1 MHz to 13 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 1 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A Condition B
Condition C
Item
8 MHz
13 MHz
16 MHz
18 MHz
Test
Symbol Min Max Min Max Min Max Min Max Unit Conditions
DMAC DREQ setup tDRQS 40 — 40 — 30 — 30 — ns Figure 21-30
time
DREQ hold
time
tDRQH 10 — 10 — 10 — 10 —
TEND delay tTED1 — 100 — 100 — 50 — 50
time 1
Figure 21-28,
Figure 21-29
TEND delay tTED2 — 100 — 100 — 50 — 50
time 2
ITU Timer output tTOCD — 100 — 100 — 100 — 100 ns Figure 21-24
delay time
Timer input
setup time
tTICS 50 — 50 — 50 — 50 —
Timer clock
tTCKS 50 — 50 — 50 — 50 —
input setup time
Figure 21-25
Timer Single tTCKWH 1.5 — 1.5 — 1.5 — 1.5 — tCYC
clock edge
pulse Both
width edges
tTCKWL 2.5
—
2.5 —
2.5 —
2.5 —
SCI Input Asyn- tSCYC 4
clock chronous
cycle Syn-
tSCYC 6
chronous
—4
—6
—4
—6
—4
—6
— tCYC Figure 21-26
—
Input clock rise tSCKr — 1.5 — 1.5 — 1.5 — 1.5
time
Input clock fall tSCKf — 1.5 — 1.5 — 1.5 — 1.5
time
Input clock
pulse width
tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tSCYC
670
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