HD6433044 Datasheet, PDF (705/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

ø
A₉ to A₁
AS
CS3 (RAS)
RD (CAS)
HWR (UW),
LWR (LW)
RFSH
T₁
T₂
t_ASD
t_CSR
t_ASD
t_RAD2
t_RAD2
t_CSR
T₃
t_SD
t_RAD3
t_SD
t_RAD3
Figure 21-11 DRAM Bus Timing (Refresh Cycle): Three-State Access
— 2WE Mode —
ø
CS₃ (RAS)
RD (CAS)
RFSH
t_CSR
t_CSR
Figure 21-12 DRAM Bus Timing (Self-Refresh Mode)
— 2WE Mode —
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