HD6433044 Datasheet, PDF (120/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

5.4.3 Interrupt Response Time
Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5-5 Interrupt Response Time
External Memory
No. Item
On-Chip
8-Bit Bus
Memory 2 States
3 States
16-Bit Bus
2 States 3 States
1 Interrupt priority
decision
2^*1
2^*1
2^*1
2^*1
2^*1
2 Maximum number
of states until end of
current instruction
1 to 23 1 to 27
1 to 31^*4
1 to 23
1 to 25^*4
3 Saving PC and CCR 4
8
to stack
12^*4
4
6^*4
4 Vector fetch
4
8
12^*4
4
6^*4
5 Instruction prefetch^*2 4
8
12^*4
4
6^*4
6 Internal processing^*3 4
4
4
4
4
Total
19 to 41 31 to 57
43 to 73
19 to 41
25 to 49
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt
service routine.
3. Internal processing after the interrupt is accepted and internal processing after prefetch.
4. The number of states increases if wait states are inserted in external memory access.
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