HD6433044 Datasheet, PDF (299/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

9.12.2 Register Descriptions
Table 9-20 summarizes the registers of port B.
Table 9-20 Port B Registers
Address* Name
H'FFD4
Port B data direction register
H'FFD6
Port B data register
Note: * Lower 16 bits of the address.
Abbreviation R/W
PBDDR
W
PBDR
R/W
Initial Value
H'00
H'00
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B. When pins are used for TPC output, the corresponding
PBDDR bits must also be set.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PB₇ DDR PB₆ DDR PB₅ DDR PB₄ DDR PB₃ DDR PB₂ DDR PB₁ DDR PB₀ DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port B data direction 7 to 0
These bits select input or output for port B pins
A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input
pin if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a PBDDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
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