HD6433044 Datasheet, PDF (513/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

14.2.3 Serial Mode Register (SMR)
Bit 7 of SMR has a different function in smart card interface mode. The related serial control
register (SCR) changes from bit 1 to bit 0. However, this function does not exist in the flash
memory version.
Bit
7
6
5
4
3
2
1
0
GM
CHR
PR
O/E STOP MP CKS1 CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W R/W R/W
Bit 7-GSM Mode (GM): Set at 0 when using the regular smart card interface. In GSM mode, set
to 1. When transmission is complete, initially the TEND flag set timing appears followed by clock
output restriction mode. Clock output restriction mode comprises serial control register bit 1 and
bit 0.
Bit 7
GM
0
1
Description
Using the regular smart card interface mode
• The TEND flag is set 12.5 etu after the beginning of the start bit
• Clock output on/off control only
Using the GSM mode smart card interface mode
• The TEND flag is set 11.0 etu after the beginning of the start bit
• Clock output on/off and fixed-high/fixed-low control
(Initial value)
Bits 6 to 0—Operate in the same way as for the normal SCI.
For details, see section 13.2.5, Serial Mode Register (SMR).
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