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HD6433044 Datasheet, PDF (672/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer
21.2.2 AC Characteristics
Bus timing parameters are listed in table 21-4. Refresh controller bus timing parameters are listed
in table 21-5. Control signal timing parameters are listed in table 21-6. Timing parameters of the
on-chip supporting modules are listed in table 21-7.
Table 21-4 Bus Timing (1)
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.15 V to 5.5 V, AVCC = 3.15 V to 5.5 V, VREF = 3.15 V to AVCC,
VSS = AVSS = 0 V, ø = 1 MHz to 13 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 1 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A Condition B
Condition C
Item
8 MHz
13 MHz
16 MHz
18 MHz
Test
Symbol Min Max Min Max Min Max Min Max Unit Conditions
Clock cycle time
tCYC
Clock pulse low width tCL
Clock pulse high width tCH
Clock rise time
tCR
Clock fall time
tCF
Address delay time
tAD
Address hold time
tAH
Address strobe delay tASD
time
125 1000 76.9 1000 62.5 1000 55.5 1000 ns
40 — 20 — 20 — 17 —
40 — 20 — 20 — 17 —
— 20 — 15 — 10 — 10
— 20 — 15 — 10 — 10
— 60 — 50 — 30 — 25
25 — 20 — 10 — 10 —
— 60 — 50 — 30 — 25
Figure 21-7,
Figure 21-8
Write strobe delay time tWSD — 60 — 50 — 30 — 25
Strobe delay time
tSD
— 60 — 50 — 30 — 25
Write data strobe pulse tWSW1* 85 — 40 — 35 — 32 —
width 1
Write data strobe pulse tWSW2* 150 — 90 — 65 — 62 —
width 2
Address setup time 1 tAS1
Address setup time 2 tAS2
Read data setup time tRDS
Read data hold time tRDH
20 — 15 — 10 — 10 —
80 — 45 — 40 — 38 —
50 — 30 — 20 — 15 —
0 —0 —0 —0 —
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