HD6433044 Datasheet, PDF (700/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

21.4 Operational Timing
This section shows timing diagrams.
21.4.1 Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 21-7 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 21-8 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 21-9 shows the timing of the external three-state access cycle with one wait state
inserted.
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