HD6433044 Datasheet, PDF (695/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Table 21-15 Timing of On-Chip Supporting Modules
Condition A: V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_REF = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 1 MHz to 8 MHz, T_a = –20°C to +75°C (regular
specifications), T_a = –40°C to +85°C (wide-range specifications)
Condition C: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_REF = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 1 MHz to 16 MHz, T_a = –20°C to +75°C (regular
specifications), T_a = –40°C to +85°C (wide-range specifications)
Item
DMAC DREQ setup time
DREQ hold time
TEND delay time 1
TEND delay time 2
ITU Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock Single edge
pulse width _{Both edges}
SCI Input clock Asynchronous
cycle
Synchronous
Input clock rise time
Input clock fall time
Input clock pulse width
Symbol
t_DRQS
t_DRQH
t_TED1
t_TED2
t_TOCD
t_TICS
t_TCKS
t_TCKWH
t_TCKWL
t_SCYC
t_SCYC
t_SCKr
t_SCKf
t_SCKW
Condition A
8 MHz
Min Max
40
—
10
—
—
100
—
100
—
100
50
—
50
—
1.5 —
2.5 —
4
—
6
—
—
1.5
—
1.5
0.4 0.6
Condition C
16 MHz
Min Max Unit
30
—
ns
10
—
—
50
—
50
—
100 ns
50
—
50
—
1.5 —
t_CYC
2.5 —
4
—
t_CYC
6
—
—
1.5
—
1.5
0.4
0.6
t_SCYC
Test
Conditions
Figure 21-30
Figure 21-28,
Figure 21-29
Figure 21-24
Figure 21-25
Figure 21-26
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