HD6433044 Datasheet, PDF (133/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Bit 5—Address 21 Enable (A21E): Enables PA₆ to be used as the A₂₁ address output pin.
Writing 0 in this bit enables A₂₁ address output from PA₆. In modes other than 3, 4, and 6 this bit
cannot be modified and PA₆ has its ordinary input/output functions.
Bit 5
A21E Description
0
PA₆ is the A₂₁ address output pin
1
PA₆ is the PA₆/TP₆/TIOCA₂ input/output pin
(Initial value)
Bits 4 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE
0
1
Description
The bus cannot be released to an external device; BREQ and BACK
can be used as input/output pins
The bus can be released to an external device
(Initial value)
6.2.6 Chip Select Control Register (CSCR)
CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals
(CS₇ to CS₄).
If a chip select signal (CS₇ to CS₄) output is selected in this register, the corresponding pin
functions as a chip select signal (CS₇ to CS₄) output, this function taking priority over other
functions. CSCR cannot be modified in single-chip mode.
Bit
7
6
5
4
3
2
1
0
CS7E CS6E CS5E CS4E —
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Chip select 7 to 4 enable
These bits enable or disable
chip select signal output
Reserved bits
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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