HD6433044 Datasheet, PDF (292/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data
for pins PA₇ to PA₀. When a bit in PADDR is set to 1, if port A is read the value of the
corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the
corresponding pin level is read.
Bit
Initial value
Read/Write
7
PA ₇
0
R/W
6
PA ₆
0
R/W
5
PA ₅
0
R/W
4
PA ₄
0
R/W
3
PA ₃
0
R/W
2
PA ₂
0
R/W
1
PA ₁
0
R/W
0
PA ₀
0
R/W
Port A data 7 to 0
These bits store data for port A pins
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
9.11.3 Pin Functions
Table 9-19 describes the selection of pin functions.
Table 9-19 Port A Pin Functions
Pin
PA₇/TP₇/
TIOCB₂/A₂₀
Pin Functions and Selection Method
The mode setting, ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to
IOB0 in TIOR2), bit NDER7 in NDERA, and bit PA₇DDR in PADDR select the pin
function as follows
Mode
ITU channel 2
settings
PA₇DDR
NDER7
Pin function
1, 2, 5, 7
3, 4, 6
(1) in table below
—
—
TIOCB₂ output
(2) in table below
0
1
1
—
0
1
PA₇
PA₇
TP₇
input output output
TIOCB₂ input*
—
—
—
A₂₀
output
Note: * TIOCB₂ input when IOB2 = 1 and PWM2 = 0.
ITU channel 2
settings
(2)
(1)
(2)
IOB2
0
1
IOB1
0
0
1
—
IOB0
0
1—
—
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