 English |
|
|
|
|
|
|
|
| HD6433044 Datasheet, PDF (707/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer | |||
| |||
| ◁ |
ø
A9 to A1
AS
CS 3 (RAS)
HWR (UCAS),
LWR (LCAS)
RD (WE)
RFSH
T1
T2
tASD
tCSR
tASD
tRAD2
tRAD2
tCSR
T3
tSD
tRAD3
tSD
tRAD3
Figure 21-14 DRAM Bus Timing (Refresh Cycle): Three-State Access
â 2CAS Mode â
ø
CS 3 (RAS)
tCSR
HWR (UCAS),
tCSR
LWR (LCAS)
RFSH
Figure 21-15 DRAM Bus Timing (Self-Refresh Mode)
â 2CAS Mode â
699
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese