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HD6433044 Datasheet, PDF (673/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer
Table 21-4 Bus Timing (cont)
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.15 V to 5.5 V, AVCC = 3.15 V to 5.5 V, VREF = 3.15 V to AVCC,
VSS = AVSS = 0 V, ø = 1 MHz to 13 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 1 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A Condition B
Condition C
8 MHz
13 MHz
16 MHz
18 MHz
Item
Symbol Min Max Min Max Min Max Min Max
Write data delay time tWDD — 75 — 75 — 60 — 55
Write data setup time 1 tWDS1 60 — 20 — 15 — 10 —
Write data setup time 2 tWDS2 5
— –10 — –5 — –10 —
Write data hold time tWDH 25 — 15 — 20 — 20 —
Read data access
time 1
tACC1* — 120 — 60 — 60 — 50
Read data access
time 2
tACC2* — 240 — 140 — 120 — 105
Read data access
time 3
tACC3* — 70 — 30 — 30 — 20
Read data access
time 4
tACC4* — 180 — 100 — 95 — 80
Precharge time
tPCH* 85 — 55 — 45 — 40 —
Wait setup time
tWTS
40 — 40 — 25 — 25 —
Wait hold time
tWTH
10 — 10 — 5
—5
—
Bus request setup ime tBRQS 40 — 40 — 40 — 40 —
Bus acknowledge
delay time 1
tBACD1 — 60 — 50 — 30 — 30
Bus acknowledge
delay time 2
tBACD2 — 60 — 50 — 30 — 30
Bus-floating time
tBZD
Note is on next page.
— 70 — 70 — 40 — 40
Test
Unit Conditions
ns Figure 21-7,
Figure 21-8
ns Figure 21-9
ns Figure 21-21
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