HD6433044 Datasheet, PDF (827/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

SYSCR—System Control Register
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
H'F2
3
2
UE NMIEG
1
0
R/W R/W
System control
1
0
— RAME
1
1
—
R/W
RAM enable
0 On-chip RAM is disabled
1 On-chip RAM is enabled
NMI edge select
0 An interrupt is requested at the falling edge of NMI
1 An interrupt is requested at the rising edge of NMI
User bit enable
0 CCR bit 6 (UI) is used as an interrupt mask bit
1 CCR bit 6 (UI) is used as a user bit
Standby timer select 2 to 0
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Standby Timer
0
0
0 Waiting time = 8,192 states
1 Waiting time = 16,384 states
1
0 Waiting time = 32,768 states
1 Waiting time = 65,536 states
1
0
0 Waiting time = 131,072 states
1 Waiting time = 1,024 states
1 — Illegal setting
Software standby
0 SLEEP instruction causes transition to sleep mode
1 SLEEP instruction causes transition to software standby mode
820