HD6433044 Datasheet, PDF (327/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or
whether GRB3 is buffered by BRB3.
Bit 1
BFB3
0
1
Description
GRB3 operates normally
GRB3 is buffered by BRB3
(Initial value)
Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or
whether GRA3 is buffered by BRA3.
Bit 0
BFA3
0
1
Description
GRA3 operates normally
GRA3 is buffered by BRA3
(Initial value)
10.2.5 Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
Bit
7
—
Initial value
1
Read/Write
—
6
5
4
3
2
1
0
—
EXB4 EXA4 EB3
EB4
EA4
EA3
1
1
1
1
1
1
1
—
R/W R/W R/W R/W R/W R/W
Reserved bits
Master enable TOCXA4, TOCXB4
These bits enable or disable output
settings for pins TOCXA₄ and TOCXB₄
Master enable TIOCA3, TIOCB3 , TIOCA4, TIOCB4
These bits enable or disable output settings for pins
TIOCA₃, TIOCB₃ , TIOCA₄, and TIOCB₄
TOER is initialized to H'FF by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
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