HD6433044 Datasheet, PDF (164/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

7.2 Register Descriptions
7.2.1 Refresh Control Register (RFSHCR)
RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh
controller.
Bit
Initial value
Read/Write
7
6
5
4
3
SRFMD PSRAME DRAME CAS/WE M9/M8
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
2
RFSHE
0
R/W
1
0
— RCYCE
1
0
—
R/W
Refresh cycle
enable
Enables or
disables
insertion of
refresh cycles
Reserved bit
Refresh pin enable
Enables refresh signal output
from the refresh pin
Address multiplex mode select
Selects the number of column address bits
Strobe mode select
Selects 2CAS or 2WE strobing of DRAM
PSRAM enable and DRAM enable
These bits enable or disable connection of pseudo-static RAM and DRAM
Self-refresh mode
Selects self-refresh mode
RFSHCR is initialized to H'02 by a reset and in hardware standby mode.
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