HD6433044 Datasheet, PDF (135/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

6.3 Operation
6.3.1 Area Division
The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the
1-Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6-2 shows a general view of the
memory map.
H'00000
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0 (128 kbytes)
Area 1 (128 kbytes)
Area 2 (128 kbytes)
Area 3 (128 kbytes)
Area 4 (128 kbytes)
Area 5 (128 kbytes)
Area 6 (128 kbytes)
Area 7 (128 kbytes)
H'000000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Area 0 (2 Mbytes)
Area 1 (2 Mbytes)
Area 2 (2 Mbytes)
Area 3 (2 Mbytes)
Area 4 (2 Mbytes)
Area 5 (2 Mbytes)
Area 6 (2 Mbytes)
Area 7 (2 Mbytes)
H'00000
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
On-chip ROM ^*1
Area 0 (128 kbytes)
Area 1 (128 kbytes)
Area 2 (128 kbytes)
Area 3 (128 kbytes)
Area 4 (128 kbytes)
Area 5 (128 kbytes)
Area 6 (128 kbytes)
Area 7 (128 kbytes)
H'000000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
On-chip ROM ^*1
Area 0 (2 Mbytes)
Area 1 (2 Mbytes)
Area 2 (2 Mbytes)
Area 3 (2 Mbytes)
Area 4 (2 Mbytes)
Area 5 (2 Mbytes)
Area 6 (2 Mbytes)
Area 7 (2 Mbytes)
On-chip RAM^*1,*2
On-chip RAM^*1,*2
On-chip RAM^*1,*2
On-chip RAM^*1,*2
External address space^*3
External address space^*3
External address space^*3
External address space^*3
H'FFFFF ^{On-chip registers*1} H'FFFFFF ^{On-chip registers*1}
H'FFFFF ^{On-chip registers*1}
H'FFFFFF ^{On-chip registers*1}
a. 1-Mbyte modes with
on-chip ROM disabled
(modes 1 and 2)
b. 16-Mbyte modes with
on-chip ROM disabled
(modes 3 and 4)
c. 1-Mbyte mode with
on-chip ROM enabled
(mode 5)
d. 16-Mbyte mode with
on-chip ROM enabled
(mode 6)
Notes: 1. The on-chip ROM, on-chip RAM, and on-chip registers have a fixed bus width and are accessed in a
fixed number of states.
2. When the RAME bit is cleared to 0 in SYSCR, this area conforms to the specifications of area 7.
3. This external address area conforms to the specifications of area 7.
Figure 6-2 Access Area Map for Modes 1 to 6
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