HD6433044 Datasheet, PDF (394/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T₂
or T₃ state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The
TCNT byte that was not written retains its previous value. See figure 10-63, which shows an
increment pulse occurring in the T₂ state of a byte write to TCNTH.
TCNTH byte write cycle
T₁
T₂
T₃
ø
Address bus
TCNTH address
Internal write signal
TCNT input clock
TCNTH
TCNTL
N
M
TCNT write data
X
X+1
X
Figure 10-63 Contention between TCNT Byte Write and Increment
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