HD6433044 Datasheet, PDF (242/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Figure 8-16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
CPU cycle
DMAC cycle
CPU
cycle DMAC cycle
T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂
ø
DREQ
Address
bus
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 8-16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode
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