HD6433044 Datasheet, PDF (515/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

14.3 Operation
14.3.1 Overview
The main features of the smart-card interface are as follows.
• One frame consists of eight data bits and a parity bit.
• In transmitting, a guard time of at least two elementary time units (2 etu) is provided between
the end of the parity bit and the start of the next frame. (An elementary time unit is the time
required to transmit one bit.)
• In receiving, if a parity error is detected, a low error signal is output for 1 etu, beginning 10.5
etu after the start bit.
• In transmitting, if an error signal is received, after at least 2 etu, the same data is
automatically transmitted again.
• Only asynchronous communication is supported. There is no synchronous communication
function.
14.3.2 Pin Connections
Figure 14-2 shows a pin connection diagram for the smart card interface.
In communication with a smart card, data is transmitted and received over the same signal line.
The TxD₀ and RxD₀ pins should both be connected to this line. The data transmission line should
be pulled up to V_CC through a resistor.
If the smart card uses the clock generated by the smart card interface, connect the SCK₀ output pin
to the card’s CLK input. If the card uses its own internal clock, this connection is unnecessary.
The reset signal should be output from one of the H8/3048 Series’ generic ports.
In addition to these pin connections, power and ground connections will normally also be
necessary.
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