HD6433044 Datasheet, PDF (762/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

DTCR0B—Data Transfer Control Register 0B
cont
• Full address mode
H'2F
DMAC0
Bit
Initial value
Read/Write
7
DTME
0
R/W
6
—
0
R/W
5
DAID
0
R/W
4
DAIDE
0
R/W
3
TMS
0
R/W
2
DTS2B
0
R/W
1
DTS1B
0
R/W
0
DTS0B
0
R/W
Data transfer select 2B to 0B
Bit 2 Bit 1 Bit 0
Data Transfer Activation Source
DTS2B DTS1B DTS0B Normal Mode
Block Transfer Mode
0
0
0 Auto-request
(burst mode)
Compare match/input capture
A from ITU channel 0
1 Not available
Compare match/input capture
A from ITU channel 1
1
0 Auto-request
(cycle-steal mode)
Compare match/input capture
A from ITU channel 2
1 Not available
Compare match/input capture
A from ITU channel 3
1
0
0 Not available
Not available
1 Not available
Not available
1
0 Falling edge of DREQ Falling edge of DREQ
1 Low level input at DREQ Not available
Transfer mode select
0 Destination is the block area in block transfer mode
1 Source is the block area in block transfer mode
Destination address increment/decrement (bit 5)
Destination address increment/decrement enable (bit 4)
Bit 5 Bit 4
DAID DAIDE Increment/Decrement Enable
0
0 MARB is held fixed
1 Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer
If DTSZ = 1, MARB is incremented by 2 after each transfer
1
0 MARB is held fixed
1 Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer
If DTSZ = 1, MARB is decremented by 2 after each transfer
Data transfer master enable
0 Data transfer is disabled
1 Data transfer is enabled
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